several changes..
1 --- Protocol Descrition ---
3 [------------------ HEADER ------------------] [- DATA -]
4 [SYNC] [COMMAND] [LENGTH_UPPER] [LENGTH_LOWER] ([DATA])
9 Commands send from the Host to the Unit start with 0xAA.
10 Commands from the unit, to the Host Computer start with 0x55.
13 Warning: A complete Packet _must_ be smaller than 64 Bytes. This is a Firmware limit!
14 Therefore, LENGTH_UPPER is always zero.
15 LENGTH_LOWER ist the number of Data bytes, following the header. The Firmware will scrap the complete package, if length is not correct.
18 Currently the following commands are implemented:
20 -- Commands used by the unit --
21 In most cases, these are replys to host initiated commands. Only CMD_SYS_IR is used 'standalone'.
23 - CMD_SYS_SYNC (0x00)-
26 - CMD_SYS_ACK (0x01) -
27 * Acknowledge command.
30 - CMD_SYS_NACK (0x02) -
34 - CMD_SYS_NIMP (0xFF) -
35 * Issued commands is not implemented.
39 * A Infrared or Key-Event has occured
40 * 2 data Bytes: RC5-Address & RC5-Command
42 -- Host initiated commands --
43 - CMD_DISP_CLEAR_SCREEN (0x10) -
45 * Clears Display Data-RAM from 0x0000 to 0x1000
47 - CMD_DISP_SET_ROW_DATA (0x14) -
48 * Required data: at least 3 data Bytes: ADDR_LOWER, ADDR_UPPER, DISPLAY_DATA[]
49 * sets the Display Ram starting from address (ADDR_UPPER << 2 + ADDR_LOWER) to DISPLAY_DATA[].
50 * most usefull if one ore more complete rows are written.
52 - CMD_DISP_SET_ADDRESS (0x16) -
53 * Required data: 2 data Bytes: ADDR_LOWER, ADDR_UPPER
54 * Sets the Display Ram Address to (ADDR_UPPER << 2 + ADDR_LOWER)
56 - CMD_WRITE_EEPROM (0x20) -
57 * Required data: 2 data Bytes: ADDR, DATA
58 * Writes DATA to the internal EEPROM at location ADDR
60 - CMD_READ_EEPROM (0x21) -
61 * Required data: 1 data Bytes: ADDR
62 * Returns one byte from the internal EEPROM at location ADDR
64 - CMD_READ_CLOCK (0x40) -
66 * Returns 10Bytes of Data, corresponding to the pcf8583 ram from 0x00 to 0x0F.
68 - CMD_WRITE_CLOCK (0x41) -
69 * Required data: 10Bytes: CLOCK_DATA[]
70 * Writes CLOCK_DATA to the pcf8583 from address 0x00 to 0x0F.
72 - CMD_SET_PWM1 (0x45) -
73 * Required data: 1 Byte (DutyCycle)
74 * Loads PWM1 DutyCycle Register
76 - CMD_SET_PWM2 (0x46) -
77 * Required data: 1 Byte (DutyCycle)
78 * Loads PWM2 DutyCycle Register
80 - CMD_SET_MODE_MANAGED (0x70) -
82 * Enters 'managed mode': now the display wont be updated, ir&key events will be send
84 - CMD_SET_MODE_UNMANAGED (0x71) -
86 * Enters 'unmanaged mode': now the display wont be updated, ir&key events will be send
90 * Enters Bootload mode. NO ACK is send!
93 0xAA 0x10 0x00 0x00 -> Clears the Display
94 0xAA 0x45 0x00 0x01 0x80 -> Sets PWM1 to 50% DC
95 0xAA 0x14 0x00 0x03 0x00 0x08 0x42 -> Writes a small 'b' to the upper left display corner
96 0xAA 0x80 0x00 0x00 -> Enters Bootloader mode
97 0xAA 0x40 0x00 0x00 -> Returns 10Bytes Clock Data